Adata 4GB DDR3 1333MHz Desktop Ram

Adata 4GB DDR3 1333MHz Desktop Ram

The Adata 4GB DDR3 1333MHz Desktop Ram module is a 512Mx72 bits 4GB(4096MB) DDR3-1333(CL9)-9-9-24 SDRAM memory module. The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9-9-9-24 at 1.35V. Adata 4GB DDR3 1333MHz module is composed of eight-teen 256Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass–epoxy printed circuit board. Adata 4GB DDR3 1333MHz module is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high-performance memory system applications.

Adata 4GB DDR3 1333MHz Desktop Ram Review

Purchased this for an older Biostar motherboard mATX. Was not sure it would match its predecessor memory of the same bandwidth and speed etc. But it did and now I have 8 gigs of solid working memory. Boosted system performance significantly. Would recommend! Good memory at a good price. Despite it's different look, it perfectly matched the other 4GB ADATA stick with heat spreader that I had, allowing me to easily upgrade my workstation to 8GB. Working at 1333MHz @ 9-9-9-24 with no issues. As other reviews already state, this RAM does its' job. The price is great, and despite being a lower frequency than other choices there isn't a performance difference. This is great RAM for cheap, I'd recommend it to anyone.

Specifications

• Power supply (Normal): VDD & VDDQ = 1.35V (1.283V to 1.45V)
• Backward-compatible to VDD=+1.5V+-0.075V
• MRS Cycle with address key programs
• - CAS Latency (6,7,8,9)
• - Burst Length (BL):8 and 4 with Burst Chop(BC)
• Bi-directional, differential data strobe (DQS and /DQS)
• Differential clock input (CK, /CK) operation
• DLL aligns DQ and DQS transition with CK transition
• Double-data-rate architecture; two data transfers per clock cycle
• 8 independent internal bank
• Internal (self) calibration: Internal self calibration through ZQ pin (RZQ:240 ohm±1%)
• Auto refresh and self refresh
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
• 8-bit pre-fetch.
• On Die Termination using ODT pin.
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM.
• EEPROM software write protect.
• Lead-free products are RoHS Compliant